The DDR3 Controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The DDR3 Controller IIP can be implemented in any technology.
The DDR3 Controller IIP core supports the protocol standard JESD79-3F specification and is compatible with DFI-version 2.0 or higher specification compliant. DDR3 controller IIP also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
The DDR3 Controller IIP is delivered in Verilog RTL that DDR3 be implemented in an ASIC or FPGA. The DDR3 Controller IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.