The DDR Controller IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The DDR Controller IIP DDR be implemented in any technology.

The DDR Controller IIP core supports the protocol standard of JESD79F specification and is compatible with DFI-version 2.0 or higher specification compliant. DDR controller IIP also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

The DDR Controller IIP is delivered in Verilog RTL that DDR be implemented in an ASIC or FPGA. The DDR Controller IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.