The eMMC Host IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The eMMC Host IIP can be implemented in any technology.
The eMMC Host IIP core supports the JESD84-B51 Specification and supporting standards. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, AXI, OCP, Wishbone, VCI, Avalon, PLB, Tilelink, Wishbone or custom buses.
The eMMC Host IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The eMMC Host IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.