The UFS HOST IP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The UFS HOST IP can be implemented in any technology.
The UFS HOST IP core is fully compliant with JESD220E UFS Specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, Wishbone, VCI, Avalon PLB, Wishbone or custom buses.
The UFS HOST IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The UFS HOST IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.