The SPMI Slave AXI Bridge IP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The SPMI Slave AXI Bridge IP can be implemented in any technology.
The Slave AXI Bridge IP core supports the SPMI 2.0 standard. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
The Slave IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Slave IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.