The MIPI UNIPRO IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The MIPI UNIPRO IP can be implemented in any technology.
The MIPI UNIPRO IIP core supports the MIPI UNIPRO Version 1.8 and 2.0 specification. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or custom buses.
The MIPI UNIPRO IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The MIPI UNIPRO IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.