The HDCP 2.x Receiver IP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The HDCP 2.x Receiver IP can be implemented in any technology.
The Receiver IP core supports the HDCP 2.2 and 2.3 standards. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, Wishbone, VCI, Avalon PLB, Wishbone or custom buses.
The Receiver IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Receiver IP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.