The HDMI Sink IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The HDMI Sink IIP can be implemented in any technology.

The HDMI Sink IIP core supports the HDMI 1.4b/2.0b/2.1 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.