The SLVS-EC Receiver IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The SLVS-EC Receiver IIP can be implemented in any technology.
The SLVS-EC Receiver IIP core supports the SLVS-EC 2.0 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB,Wishbone or custom buses.
The SLVS-EC Receiver IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The SLVS-EC Receiver IIP is validated in using FPGA. The Receiver core includes RTL code, test scripts and a test environment for complete simulation.