The SMPTE SDI Receiver IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The SMPTE SDI Receiver IIP can be implemented in any technology.
The SMPTE SDI Receiver IIP core supports the SMPTE SDI 2.2A standard. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, VCI, Avalon PLB, Wishbone, Tilelink or custom buses.
The SMPTE SDI Receiver IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The SMPTE SDI Receiver IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.