The V-By-One Receiver IIP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The V-By-One Receiver IIP can be implemented in any technology.
The V-By-One Receiver IIP core supports the VByOne 1.2/1.3/1.4 specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI, Avalon,PLB,Wishbone or custom buses.
The V-By-One Receiver IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The V-By-One Receiver IIP is validated in using FPGA. The Receiver core includes RTL code, test scripts and a test environment for complete simulation.