The AC’97 controller IIP Core is full-featured, easy-to-use, synthesizable designs that are easily integrated into any SoC or FPGA development. The AC’97 controller IIP can be implemented in any technology.
The AC’97 controller IIP core supports the AC’97 2.2 standard. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, Wishbone, VCI, Avalon PLB, Wishbone or custom buses.
The AC’97 controller IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The AC’97 controller IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.