The Octal SPI master IP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The Octal SPI master IP can be implemented in any technology.
The Octal SPI master IP core supports the SPI Blocks specs with 8 bit data width. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
The Octal SPI Master IP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. Octal SPI Master IP is validated using FPGA. The core incluades RTL code, test scripts and a test environment for complete simulation.