The eSPI Slave SOC IIP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The eSPI Slave SOC IIP can be implemented in any technology.
The eSPI Slave SOC IIP core supports the Standard eSPI Specification revision 1.0. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
The eSPI Slave SOC IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The eSPI Slave SOC IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.