The Interlaken IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The Interlaken IIP can be implemented in any technology.

The Interlaken IIP core supports the Interlaken protocol specification v1.2, Interlaken look as side protocol 1.1, Interlaken retransmission extension specification 1.2, Interlaken Reed-Solomon Forward Error Correction Extension 1.1, Interlaken Interoperability Recommendations 1.11 and Interlaken Dual Calendar Extension 1.0. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses. DMA engine can be incorporated based on requirement.

The Interlaken IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Interlaken IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.