The Ethernet Switch IIP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The Ethernet Switch IIP can be implemented in any technology.
The Ethernet Switch IIP core supports a non-blocking crossbar matrix that allows continuous transfers between all the ports. It implements a store and forward switching approach that fulfills Ethernet standard policy regarding frame integrity checking. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses .
The Ethernet Switch IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Ethernet Switch IIP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.